Patent · US Active

Method and apparatus for balanced shield shunts, leads and pads for electrical noise reduction in read heads

US7508613B2 · kind B2 · utility

2Cited by

5References

20Claims

0Family size

Assignee

Hitachi Global Storage Technologies Netherlands B.V. · NL

Inventors

Edward Hin Pong Lee · San Jose, US
Robert Langland Smith · Cupertino, US

Key dates

Filing date	Mar 15, 2007
Grant date	Mar 24, 2009
Priority date	—
Expiry date	Mar 15, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG11B2005/0016
WIPO fieldAudio-visual technology
WIPO sectorElectrical engineering

Abstract

A symmetrical read element circuit for reducing electrical and magnetic noise using signal processing, such as a differential preamplifier. The circuits are symmetrically created on both sides of the read element so that the noise is balanced on both sides of the read element to allow substantial noise reduction by the signal processing.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.