Method for fault handling in a converter circuit for wiring of three voltage levels
US7508640B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2006 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | May 21, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M1/32
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The document specifies a method for fault handling in a converter circuit for switching three voltage levels, in which the converter circuit has a converter subsystem provided for each phase (R,S,T), in which a top fault current path (A) or a bottom fault current path (B) in the converter subsystem is detected, the top fault current path (A) running through the first, second, third and sixth power semiconductor switches in the converter subsystem or through the first and fifth power semiconductor switches (S1, S5) in the converter subsystem, and the bottom fault current path (B) running through the second, third, fourth and fifth power semiconductor switches in the converter subsystem or through the fourth and sixth power semiconductor switches in the converter subsystem, and in which the power semiconductor switches are switched on the basis of a fault switching sequence. To avoid phase shorting of all the phases of the converter circuit in order to achieve a safe operating state for the converter circuit in the event of a fault, the fault switching sequence in the event of detection of the top or the bottom fault current path (A, B) is initially followed by the detection's accomp…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.