Non-volatile semiconductor storage system
US7508704B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2007 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | Sep 12, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5646
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control the bit-lines. A word line control circuit applies a plural-bit data read voltage as a word line voltage to the word line. The plural-bit data read voltage is larger than an upper limit of one of plural threshold voltage distributions and smaller than a lower limit of another threshold voltage distribution. Furthermore, it applies a soft-value read voltage as a word line voltage to the word line. The soft-value read voltage is smaller than an upper limit of a threshold voltage distribution and larger than a lower limit thereof. The likelihood calculation circuit calculates likelihood of the plural-bit data stores in the memory cells based on the soft-value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.