Semiconductor memory asynchronous pipeline
US7509469B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 12, 2007 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | Feb 12, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.