Dynamic frequency scaling for JTAG communication
US7509549B2 · kind B2 · utility
26Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2006 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | Aug 1, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2242
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system comprising a system under test (SUT) having a control logic. The SUT further comprises testing logic coupled to the SUT and adapted to provide to the SUT a clock signal to facilitate communications between the testing logic and the SUT. The control logic monitors a number of activated processors in a scan chain coupled to the control logic. If the number of activated processors is reduced, the control logic dynamically decreases a frequency of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.