Apparatus and method for parity generation in a data-packing device
US7509559B2 · kind B2 · utility
1Cited by
8References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 27, 2005 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | Feb 28, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data-packing device, such as a direct memory access controller (DMA), aligns data at a granularity smaller than an error protected unit (EPU) encoded by an error correction code (ECC) in the memory. For example, the data alignment is at a double-word level or a byte level. The data-packing device reads data from the memory, shifting the data, and marks a good data unit as corrupted if the data unit constitutes a fractional portion of a corrupted EPU. The marking of the data unit is performed by inverting a parity bit of the data unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.