Maintaining data integrity for extended drop outs across high-speed serial links
US7509562B1 · kind B1 · utility
3Cited by
11References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2004 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | Aug 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0079
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Improved error correction techniques and circuitry are provided. The error correction circuitry may be integrated with a programmable logic device (PLD), or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of providing data recovery during extended drop out periods of a high speed serial link with an embedded clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.