Method of manufacturing a semiconductor device having damascene structures with air gaps
US7510959B2 · kind B2 · utility
1Cited by
4References
12Claims
0Family size
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Key dates
| Filing date | Mar 16, 2005 |
| Grant date | Mar 31, 2009 |
| Priority date | — |
| Expiry date | Jan 11, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises the steps of depositing and patterning a disposable layer, depositing a first barrier layer on top of the patterned disposable layer, depositing a metal layer, planarizing the metal layer, depositing a second barrier layer, planarizing the second barrier layer until substantially no barrier layer material is present on top of the disposable layer, depositing a permeable layer, removing the disposable layer through the permeable layer to form air gaps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.