Cap for semiconductor device package, and manufacturing method thereof
US7510968B2 · kind B2 · utility
1Cited by
4References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2006 |
| Grant date | Mar 31, 2009 |
| Priority date | — |
| Expiry date | May 16, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01079
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A cap for a semiconductor device package, including a body formed at a predetermined thickness with a cavity. The cap further includes a first seed layer formed on an inner circumference of a first via hole formed at a predetermined depth from the cavity formation surface of the body, a second seed layer formed on an inner circumference of a second via hole formed at a predetermined depth from the opposite surface to the cavity formation surface of the body, and plating materials filled in the first via hole and the second via hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.