Bulk resistance control technique

US7511345B2 · kind B2 · utility

Assignees

• Sarnoff Corporation · US
• Sarnoff Europe · BE

Inventors

• Benjamin Van Camp · Brugge, BE
• Gerd Vermont · Ruiselede, BE

Key dates

• Filing date: Jun 12, 2006
• Grant date: Mar 31, 2009
• Expiry date: Jul 25, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/815

Abstract

The present invention provides a MOS transistor device for providing ESD protection including at least one interleaved finger having a source, drain and gate region formed over a channel region disposed between the source and the drain regions. The transistor device further includes at least one isolation gate formed in at least one of the interleaved fingers. The device can further include a bulk connection coupled to at least one of the source, drain and gate regions via through at least one of diode, MOS, resistor, capacitor inductor, short, etc. The bulk connection is preferably isolated through the isolation gate.