Patent · US Active

Methods and apparatus to test power transistors

US7511527B1 · kind B1 · utility

4Cited by

4References

20Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Kee Chee Tiew · Richardson, US
Brett Smith · McKinney, US

Key dates

Filing date	Jan 29, 2008
Grant date	Mar 31, 2009
Priority date	—
Expiry date	Jan 29, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/2831
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

Methods and apparatus to test power transistors of integrated circuits on a wafer are disclosed. An example method comprises measuring a drain-source on resistance of a first transistor, measuring a drain-source on resistance of a second transistor, computing a scaling ratio between the transistors based on the drain-source on resistances of the transistors, measuring a first current indicative of an over-current condition of the first transistor, and computing a second current of the second transistor based on the current of the second transistor and the scaling ratio.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.