Phase lock loop and operating method thereof
US7511579B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2006 |
| Grant date | Mar 31, 2009 |
| Priority date | — |
| Expiry date | Aug 20, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1972
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLL is provided, comprising a first divider, a PFD, a loop filter, a VCO, a second divider and a controller. The first divider receives a reference signal and divides the reference signal by R to obtain a divided signal. The PFD compares the divided signal and a feedback signal to generate a compared The VCO selects one of a plurality of operating curves for oscillation based on a selection signal, and generates an oscillation signal based on an operating voltage generated by signal the loop filter. The second divider divides the oscillation signal by N to obtain the feedback signal. The controller operates in an initial mode to recursively determine the selection signal by calculating differences of the feedback signal and the divided signal. When the selection signal converges to stable, the PLL switches to a normal mode to operate on the corresponding operating curve.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.