Switch circuit and integrated circuit
US7511592B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2006 |
| Grant date | Mar 31, 2009 |
| Priority date | — |
| Expiry date | Dec 18, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/76
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A switch circuit includes a balanced line connected between one end of an unbalanced line having another end connected to an input terminal and an output terminal and a balanced line connected between the one end of the unbalanced line and an output terminal. On each of the balanced lines, a plurality of quarter-wave transmission lines are connected in cascade, and each of a plurality of FETs, whose impedance is controllable, is connected between one pair of transmission lines constituting a balanced line for each interconnection point between the transmission lines, so that the power of a signal is distributed to both of the pair of transmission lines, and therefore the inputted power becomes half on each balanced line, thereby making it possible to prevent a DC-like current from flowing when the FET is in an off state even if a high frequency signal with high power is inputted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.