Semiconductor memory device
US7511985B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2007 |
| Grant date | Mar 31, 2009 |
| Priority date | — |
| Expiry date | Sep 14, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprises a array of memory cells arranged in a matrix, each memory cell connected to one end of a variable resistor element where the electric resistance is shifted from the first state to the second state by applying the first writing voltage and from the second state to the first state by applying the second writing voltage, and the source or drain of the selecting transistor. The second writing time for the second writing action of shifting the electric resistance of the variable resistor element from the second state to the first state is longer than the first writing time of shifting the same reversely. The second number of the memory cells subjected to the second writing action at once is greater than the first memory cell number subjected to the first writing action at once, and at least the second number is two or more.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.