Multi-channel synchronization architecture
US7512201B2 · kind B2 · utility
5Cited by
41References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2005 |
| Grant date | Mar 31, 2009 |
| Priority date | — |
| Expiry date | Feb 9, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0091
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention provides a robust global timing resynchronization architecture, a multi-link communications system including the same, and a method for minimizing the effects of resynchronization signal skew, reference clock skew, and PLL static phase error variations on resynchronization of multi-link communications systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.