Data cleaning with an asynchronous reference clock
US7512203B2 · kind B2 · utility
2Cited by
17References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2005 |
| Grant date | Mar 31, 2009 |
| Priority date | — |
| Expiry date | Nov 18, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention may provide for independent setting of jitter tolerance and jitter transfer levels, and reduced jitter generation of a data transmission device, such as a clock and data recovery (CDR) circuit or the like. An architecture may provide for reconfigurability of a circuit for use in various applications. The architecture may include a multi-loop structure, such as a tri-loop structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.