Multi-phase-locked loop (PLL) solution for multi-link multi-rate line card applications
US7512204B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2005 |
| Grant date | Mar 31, 2009 |
| Priority date | — |
| Expiry date | Mar 5, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/23
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-phase-locked loop (PLL) solution is described for multi-link multi-rate line cards. A reconfigurable enhanced phase-locked loop (EPLL) associated with a particular port in a line card is cascaded with an fast phase-locked loop (FPLL) and their combined output is used to provide a sampling clock to a data handler such as a serializer/deserializer (SERDES). The enhanced phase-locked loop (EPLL) is operable to take a multi-rate clock input and scale it accordingly to provide a fixed rate clock to the fast phase-locked loop (FPLL) input. The enhanced phase-locked loop (EPLL) can be dynamically reconfigured without affecting operation of other ports in the line card. The fast phase-locked loop (FPLL) and serializer/deserializer (SERDES) sample link data at a fixed rate and pass the data down through the communication system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.