Context switching using halt sequencing protocol
US7512773B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2005 |
| Grant date | Mar 31, 2009 |
| Priority date | — |
| Expiry date | Jun 25, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A halt sequencing protocol permits a context switch to occur in a processing pipeline even before all units of the processing pipeline are idle. The context switch method based on the halt sequencing protocol includes the steps of issuing a halt request signal to the units of a processing pipeline, monitoring the status of each of the units, and freezing the states of all of the units when they are either idle or halted. Then, the states of the units, which pertain to the thread that has been halted, are dumped into memory, and the units are restored with states corresponding to a different thread that is to be executed after the context switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.