Semiconductor memory device and method for stacking reference data
US7512845B2 · kind B2 · utility
11Cited by
10References
20Claims
0Family size
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Key dates
| Filing date | Jun 9, 2004 |
| Grant date | Mar 31, 2009 |
| Priority date | — |
| Expiry date | Aug 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/38
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device for compensating latency by stacking reference data. The semiconductor memory device compensates the latency and test errors between two signals by detecting the latency of the two signals and stacking the reference data without using an extra signal. Accordingly, a system can be simplified and power consumption can be reduced when testing the semiconductor memory device, since the extra circuit is unnecessary to synchronize a data sync signal with output data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.