Method and apparatus for testing, characterizing and monitoring a chip interface using a second data path
US7512854B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2005 |
| Grant date | Mar 31, 2009 |
| Priority date | — |
| Expiry date | Apr 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data receiver circuit in a receiving chip provides the capability to characterize an interface, which includes one or more inter-chip communication lines, between a transmitting chip and the receiving chip by transmitting the data across a primary data path and a secondary data path, latching the data in the secondary data path using a clock signal that is skewed relative to a clock signal used to latch the primary data path, comparing the data latched from the primary and secondary data paths, and recording errors. Because the primary data path is not impacted by the test cycle, the test cycle may be run while data associated with applications running on the system are transmitted across the inter-chip communication lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.