Method for fabricating nanocoils
US7514301B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2006 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | Dec 7, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method for fabricating nanocoils and improved nanocoils fabricated therefrom. Embodiments of the method utilizing deep reactive ion etching (DRIE). A method for fabricating nanocoils includes providing a silicon-on-insulator (SOI) wafer, in which SOI wafer includes buried oxide layer, patterning one or more devices into a layer of silicon on top of the buried oxide layer, depositing tensile stressed nitride layer on the top silicon layer, patterning coiling arm structure on top silicon layer, patterning an overlapping etch window mask on bottom side of SOI wafer using, in which patterning overlapping etch window mask removes SOI wafer and exposes buried oxide layer in width greater than coiling arm structure, and releasing coiling arm structure so that coiling arm coils to form nanocoil. In embodiments, DRIE is utilized to pattern the overlapping etch window mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.