Methods to selectively protect NMOS regions, PMOS regions, and gate layers during EPI process
US7514309B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2005 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | Jul 19, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
A semiconductor device is fabricated with a protective liner and/or layer. Well regions and isolation regions are formed within a semiconductor body. A gate dielectric layer is formed over the semiconductor body. A gate electrode layer, such as polysilicon, is formed on the gate dielectric layer. A protective gate liner is formed on the gate electrode layer. A resist mask is formed that defines gate structures. The gate electrode layer is patterned to form the gate structures. Offset spacers are formed on lateral edges of the gate structures and extension regions are then formed in the well regions. Sidewall spacers are then formed on the lateral edges of the gate structures. An NMOS protective region layer is formed that covers the NMOS region of the device. A recess etch is performed within the PMOS region followed by formation of strain inducing recess structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.