Semiconductor device
US7514766B2 · kind B2 · utility
108Cited by
6References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 3, 2006 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | Jan 17, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device in which the threshold voltage of transistors is controlled through the applied substrate bias and having relatively small size. The semiconductor device includes: a clock signal line; a shield wiring for shielding the clock signal line from another interconnection; and a substrate bias generating circuit. The substrate bias is applied through the shield wiring to a region on which a transistor is formed. The threshold voltage of the transistor depends to the substrate bias applied to the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.