Semiconductor integrated circuit having improved power supply wiring
US7514795B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 20, 2005 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | Mar 4, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor integrated circuit including a plurality of cells, a supplementary power-supply wire is disposed between a lattice-shaped upper power-supply wire and a lower cell power-supply wire for cases in which power is supplied from the upper power-supply wire to the lower cell power-supply wire. The supplementary power-supply wire and the lower cell power-supply wire are connected by two vias. The supplementary power-supply wire and the upper power-supply wire are connected by a single via. Current from the supplementary power-supply wire is divided by the two vias and then supplied to the lower cell power-supply wire. Therefore, when power is supplied from the upper power-supply wire to the lower cell power-supply wire, current concentration at the connection points of the lower cell power-supply wire to the vias is decreased, thereby reducing wire breaks caused by EM (electro migration).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.