Electronic network circuit with dissymmetrical differential pairs
US7515085B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2006 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | Jun 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/362
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention relates to integrated circuits comprising a set of identical differential pairs of two transistors each (T1, T2; T3, T4) one receiving a variable voltage (Vinp, Vinn) at its base and the other receiving a fixed reference voltage (Vrefp, Vrefn). In order to reduce the dispersion of the offset voltages of said differential pairs, it is provided that the transistor (T2, T4) that receives a fixed reference voltage has an emitter surface at least twice as large as the transistor (T1, T3) that receives a variable voltage at its base. Application to signal folding circuits and to analog-to-digital converters using differential pairs of transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.