System and method to relieve ESD requirements of NMOS transistors
US7515390B2 · kind B2 · utility
2Cited by
9References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 24, 2003 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | Dec 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/08142
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method relieves ESD requirements on devices in circuits of chips that are susceptible to being damaged from ESD through an external pad. For example, one of the devices can be NMOS transistors having drains (or sources) connected to the external pad(s) and no (or significantly small) current flows from their drains (or sources) to the corresponding pad(s). In order to protect such a device, an ESD protecting system is coupled between the NMOS device and the pad. The ESD protecting system can include an n-type transistor or a p-type transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.