CMOS logic compatible non-volatile memory cell structure, operation, and array configuration
US7515478B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2007 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | Aug 20, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is to provide a logic based single-poly non-volatile memory cell which is compatible with the CMOS process, uses lower voltages for operating, and is more reliable in program, read, or erase operation. A non-volatile memory cell in accordance with the present invention comprises a program transistor with a program transistor source as a first program terminal; a select transistor with a select transistor gate as a select terminal and a select transistor drain as a second program terminal; and an erase transistor with an erase transistor source and an erase transistor drain connected as an erase terminal, wherein the erase transistor shares a floating gate with the program transistor and the drain program transistor is connected to the select transistor source. By employing the present invention, significant cost advantages in feature-rich semiconductor products, such as System-on-Chip (SoC) design, compared to conventional dual-poly floating gate embedded Flash memory are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.