Transmitter, receiver, and methods
US7515604B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 3, 2003 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | Sep 6, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/168
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A computer capable of performing communications processing using a protocol at high speed in simple and low cost configuration is provided. After an SD-RAM controller stores AV data inputted via an AV interface in an AV buffer circuit, a packet processing unit, for example, generates jumbo packet data of 32 KB. A PCI bus interface outputs data required for transmitting processing of the jumbo packet data to a CPU, and the CPU generates header data. A packet processing unit, according to the header data, splits the jumbo packet data and generates Ethernet packet data of a maximum of 1518 byte. The SD-RAM controller transmits the applicable data from a MAC circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.