Method evaluating threshold level of a data cell in a memory device
US7516037B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2007 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | May 31, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus; includes the steps of: (a) in no particular order; (1) selecting a test threshold signal; and (2) setting a read signal at a non-read level; (b) applying the test threshold signal to the programming locus; (c) cycling the read signal between a read level and a non-read level while applying the test threshold signal to the programming locus to present at least two test signals at the read locus when the read signal is at the read level; and (d) while cycling, observing whether the at least two test signals manifest a difference greater than a predetermined amount.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.