Distributed processing architecture with scalable processing layers
US7516320B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2006 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | Jul 8, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a system on chip having a scalable, distributed processing architecture and memory capabilities through a plurality of parallel processing layers. In one embodiment, the processor comprises a plurality of processing layers, a processing layer controller, and a central direct memory access controller. The processing layer controller manages the scheduling of tasks and distribution of processing tasks to each processing layer. Within each processing layer, a plurality of pipelined processing units (Pus), specially designed for conducting a defined set of processing tasks, are in communication with program memories and data memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.