System and method for testing an on-chip initialization counter circuit
US7516377B1 · kind B1 · utility
2Cited by
3References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 1, 2006 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | Jun 23, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31724
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus and method is disclosed for providing automated testing for an on-chip initialization counter circuit that comprises a plurality of counter flip-flop circuits that are used in the initialization of an integrated circuit. The apparatus comprises a state machine and a state machine counter circuit. The state machine receives signals from the initialization counter circuit and utilizes the signals to create a built-in self test output signal that indicates a current state within the initialization counter circuit. The state machine is capable of testing various operational states of an initialization counter circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.