Input capacitance characterization method in IP library
US7516427B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Aug 5, 2005 |
| Grant date | Apr 7, 2009 |
| Priority date | — |
| Expiry date | Oct 15, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A methodology for characterization of an IP (Intellectual Property) component is provided. Digital pins are recognized by skipping analog pins and special IO pins. First two layers of the IP component are classified in response to connection of the input pins. Partial circuits of the IP component are extracted for simulation. Three corners of IP library are generated. Therefore, input capacitance of the IP component is simulated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.