Independently-double-gated field effect transistor
US7518189B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2006 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Nov 8, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/873
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This independent double-gated transistor architecture creates a MOSFET, JFET or MESFET in parallel with a JFET. Its two gates may be configured to provide a four-terminal device for independent gate control, a floating gate device, and a double-gate device. First and second insulating spacers are disposed on opposing sides of the top gate with the first spacer between the source and the top gate and the second spacer between the drain and the top gate. Source and drain extensions extend proximate to the spacers and couple to the channel. The spacers shield the channel from the field effect of the source and drain and further resist compression of the channel by the source and drain. Truly independent control of the two gates makes possible many 2-, 3- and 4-terminal device configurations that may be dynamically reconfigured to trade off speed against power. The resulting transistors exhibit inherent radiation tolerance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.