Package level voltage sensing of a power gated die
US7518355B2 · kind B2 · utility
9Cited by
7References
11Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 30, 2007 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Apr 9, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for voltage sensing at active power gated cores of a multi core CPU wherein a Controlled Collapse Chip Carrier bump in a gating region for an associated core is isolatable from an ungated power region by a power gate to allow voltage sensing at a designated location with substantially no current passing there through.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.