Ratio granularity clock divider circuit and method
US7518418B1 · kind B1 · utility
0Cited by
9References
21Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 25, 2007 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Sep 25, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/68
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a ratio clock divider comprises circuitry for producing an input signal from a differential clock signal, part of which includes circuitry for extending a clock phase of the differential clock signal every Ith cycle to produce the input signal, I being an integer. The ratio clock divider also includes circuitry for dividing the frequency of the input signal by I to produce a divided clock signal. The divided clock signal has a frequency that equals the frequency of the differential clock signal divided by N, N being equal to I plus a fraction F.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.