Low power flip-flop circuit and operation
US7518426B1 · kind B1 · utility
8Cited by
3References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 16, 2007 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Mar 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low power flip-flop circuit and its operation are described. In one example, the circuit includes a clocked gate for producing an output in response to an input when a clock is received, and a clock control circuit to receive the clock and the input, to determine whether the output will be changed by the input and to provide the clock to the clocked gate if the output will be changed by the input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.