Over-voltage tolerant ESD protection circuit
US7518844B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2006 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Mar 18, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H1/04
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An ESD protection circuit for over-voltage signal bus is disclosed that includes a diode circuit that is electrically connected to a pseudo power supply circuit. The pseudo power supply circuit includes a pseudo first power supply line coupling to an actual first power supply line having a first voltage supply level and a pseudo second power supply line coupling to an actual second power supply line having a second voltage supply level. The pseudo first power supply line and the pseudo second power supply line are clamped by an ESD clamping circuit such that the ESD protection circuit discharges voltage when an ESD event occurs, and does not interfere with the internal circuit when an over-voltage occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.