ESD protection method for low-breakdown integrated circuit
US7518846B1 · kind B1 · utility
6Cited by
3References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 10, 2006 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Mar 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/711
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An ESD protection device has a multi-stage RC-timed architecture to turn on quickly and sink current for a relatively long time period. For example, a high power voltage clamp and a low power voltage clamp coupled in parallel to protect internal circuitry of an integrated circuit. The high power clamp turns on during the first few microseconds of an ESD event, and sinks current for a brief period of time, during which the low power clamp turns on as well. Once the high power clamp turns off, the low power clamp continues to sink current until a safe level is reached.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.