Interposer containing bypass capacitors for reducing voltage noise in an IC device
US7518881B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 20, 2007 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Jul 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides an apparatus that reduces voltage noise for an integrated circuit (IC) device. This apparatus includes an interposer, which is configured to be sandwiched between the IC device and a circuit board. This interposer has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the IC device. A plurality of bypass capacitors are integrated into the interposer and are coupled between the power and ground connections for the IC device, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.