Semiconductor memory device and semiconductor integrated circuit system
US7518903B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2007 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Mar 28, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory device including resistance change memory devices, when a resistance change memory device is in standby mode, the two terminals of the resistance change memory device, i.e., a bit line and a source line, are set at a precharge potential Vp, respectively. At the time of a set operation, the bit line is set to a set voltage Vd, which is higher than the precharge potential Vp, while the source line is grounded. At the time of a reset operation, bit line is grounded, while the source line is set to the set voltage Vd. At the time of a data-read operation, the source line is grounded by a read bias generation circuit, while the potential of the bit line is kept at the precharge potential Vp.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.