Semiconductor memory device which includes memory cell having charge accumulation layer and control gate

US7518921B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Hiroshi Maejima · Tokyo, JP
• Makoto Hamada · Miki, JP

Key dates

• Filing date: Mar 20, 2007
• Grant date: Apr 14, 2009
• Expiry date: May 14, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A semiconductor memory device includes a memory cell array, a word line, a source line, a row decoder, and a source line driver circuit. The memory cell array includes a memory cell unit having a plurality of memory cells connected in series. The word line is connected to control gates of the memory cells. The source line is electrically connected to sources of the memory cells positioned on one end sides of the memory cell unit. The row decoder selects the word line. The source line driver circuit is arranged in the row decoder and applies a first voltage to the source line.