Erase cycle counting in non-volatile memories
US7518932B2 · kind B2 · utility
4Cited by
6References
26Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 22, 2006 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Dec 22, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0246
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Erase cycle counting may be used for a non-volatile memory to balance the cycles on memory blocks or partitions. In some embodiments, the non-volatile memory may include two memory locations such as wordlines associated with each block of memory. The wordlines may be alternately erased so that an updated cycle count is transferred from the wordlines to the other. In the case of a power loss in the course of the updating of the cycle count, a method may detect that the data is in improper states and require that the erase be restarted after the power loss in order to recover the correct erase cycle count.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.