Memory control device
US7518946B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 12, 2007 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Oct 3, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory control device is disclosed that comprises a clock generator that generates a reference clock, a DLL circuit that receives the reference clock from the clock generator and outputs an output value indicative of a clock cycle of the reference clock, a delay setting circuit that receives the output value from the DLL circuit and outputs a delay setting value based on the output value according to at least one parameter, and plural delay elements that receive the delay setting value and introduce a delay responsive to the delay setting value. One or more of the delay elements receive input signals from corresponding one or more flip-flops driven by drive clocks generated by the clock generator, and send output signals to corresponding one or more output buffers that are to be connected to a memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.