Clock EMI reduction
US7519120B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2005 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Jul 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K9/0066
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
EMI emissions generated by clock signals in a multi-slot electronic system are reduced by providing out-of-phase clock signals to alternate slots, which cause EMI emissions at typical testing distances and farther to be reduced. An electronic equipment comprises a plurality of slots, each slot operable to receive a clock signal and a plurality of phases of the clock signal, wherein a first phase of the clock signal is routed to a portion of the slots and a second phase of the clock signal is routed to a different portion of the slots. The second phase of the clock signal may be substantially 180° out-of-phase with the first phase of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.