System and method for providing a decimal multiply algorithm using a double adder
US7519647B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2005 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Mar 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4911
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for performing decimal multiplication including input registers for inputting a multiplier and a multiplicand. The multiplier includes one or more digits. The system also includes one or more two cycle adders and mechanism. The mechanism receives the multiplier and the multiplicand into the input registers. A running sum is reset to zero. The mechanism also performs for each of the digits in the multiplier in order from least significant digit to most significant digit: creating a partial product of the digit and the multiplicand; and adding the partial product to the running sum using the two cycle adders. When the loop is completed for each of the digits in the multiplier, the mechanism outputs the running sum as the result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.