Linear burst mode synchronizer for passive optical networks
US7519750B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2006 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Nov 13, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2007/047
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble. The present invention is advantageous in that the receiver circuit improves synchronized jitter performance over the prior art solutions so that additional timing margin is provided, thereby…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.