System and method for processing memory instructions using a forced order queue
US7519771B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2003 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Mar 20, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0859
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel system and method for processing memory instructions. One embodiment of the invention provides a method for processing a memory instruction. In this embodiment, the method includes obtaining a memory request; storing the memory request in an Initial Request Queue (IRQ); and processing the memory request from the IRQ by a cache controller, wherein processing includes: identifying a type of the memory request, and processing the memory request in both a local cache and an Force Order Queue (FOQ), wherein processing includes determining if a portion of an address associated with the memory request matches one or more partial addresses in the FOQ and, if the memory request misses in the cache and the address does not match one or more partial addresses in the FOQ, adding the memory request to the FOQ and allocating a cache line in the local cache corresponding to the local cache miss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.