Efficient utilization of a store buffer using counters
US7519796B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2004 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Jun 19, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3873
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for efficiently managing store buffer operations is described in connection with a multithreaded multiprocessor chip. A CMT processor keeps track of stores by maintaining two store counters in the instruction fetch unit (IFU). A speculative store counter in the IFU tracks stores in flight to the store buffer as well as stores already in the store buffer. A committed store counter in the IFU tracks the number of stores actually in the store buffer. The store buffer provides allocate and deallocate signals to accurately maintain the committed store counter. The IFU stops issuing stores to the store buffer once the speculative counter has reached a threshold value. Upon a flush, the IFU sets the speculative counter equal to the committed store counter. In this way, an efficient feedback mechanism is provided for preventing store buffer overflow that minimizes the store buffer size, operations time and power usage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.