PVT drift compensation
US7519844B2 · kind B2 · utility
12Cited by
3References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2005 |
| Grant date | Apr 14, 2009 |
| Priority date | — |
| Expiry date | Jun 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0079
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A timing circuit for generating a timing signal having a predetermined relationship with a reference signal. The timing circuit includes a locked loop for generating the recovered clock signal, comparing the phase of the reference signal to the phase of the timing signal, and adjusting the phase of the timing signal based on the comparison; and a PVT (Process-Voltage-Temperature) line operatively associated with the locked loop so that PVT drift in the PVT line counters PVT drift in the locked loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.