Method of fabricating a double gate field effect transistor device, and such a double gate field effect transistor device
US7521323B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2004 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Oct 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6739
Abstract
The present invention discloses a method of forming a double gate field effect transistor device, and such a device formed with the method. One starts with a semiconductor-on-insulator substrate, and forms a first gate, source, drain and extensions, and prepares the second gate. Then the substrate is bonded to a second carrier, exposing a second side of the semiconductor layer. Next, an annealing step is performed as a diffusionless annealing, which has the advantage that the semiconductor layer not only has a substantially even thickness, but also has a substantially flat surface. This ensures the best possible annealing action of said annealing step. Very sharp abruptness of the extensions is achieved, with very high activation of the dopants.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.